library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Tester is port( a, b: in unsigned(15 downto 0); -- two input numbers from ALU ia, ib: in unsigned(15 downto 0); -- two input numbers from I2C slaveIn ctrl: in unsigned(3 downto 0); -- opcode from ALU ictrl: in unsigned(3 downto 0); -- opcode from I2C slaveIn r: in unsigned(15 downto 0); -- result from ALU ir: in unsigned(15 downto 0); -- result from I2C slaveOut error: out std_logic_vector(5 downto 0)); -- Tester output end Tester; architecture Tester_impl of Tester is signal result : unsigned(15 downto 0); begin with ictrl select result <= a + b when X"0", -- addition a - b when X"1", -- subtraction resize(a * b, 16) when X"2", -- multiplication a / b when X"3", -- division a + 1 when X"4", -- increment a - 1 when X"5", -- decrement not a when X"6", -- bitwise NOT a and b when X"7", -- bitwise AND a xor b when X"8", -- bitwise XOR a srl to_integer(b) when X"9", -- shift right with zero padding a sll to_integer(b) when X"A", -- shift left a ror to_integer(b) when X"B", -- rotate right a rol to_integer(b) when X"C", -- rotate left X"0000" when others; -- input short error(0) <= '1' when (a /= ia and (a = b or a = ctrl)) or (b /= ib and (b = a or b = ctrl)) else '0'; -- input open error(1) <= '1' when (a /= ia and a = X"0000") or (b /= ib and b = X"0000") or (ctrl /= ictrl and ctrl = X"0000") else '0'; -- output short error(2) <= '1' when (r /= ir) and (ir /= X"0000") else '0'; -- output open error(3) <= '1' when (r /= ir) and (ir = X"0000") else '0'; -- mathematic computation error error(4) <= '1' when (ictrl < X"6") and (r /= result) else '0'; -- logical operation error error(5) <= '1' when (ictrl > X"5") and (r /= result) else '0'; end Tester_impl;