library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity I2C_ALU is port( scl_i, sda_i : in std_logic; scl_o, sda_o : out std_logic; input1_addr : in std_logic_vector(6 downto 0); input2_addr : in std_logic_vector(6 downto 0); control_addr : in std_logic_vector(6 downto 0); result_addr : in std_logic_vector(6 downto 0)); end I2C_ALU; architecture I2C_ALU_impl of I2C_ALU is component ALU is port( a, b: in unsigned(15 downto 0); -- two input numbers ctrl: in unsigned(3 downto 0); -- opcode r: out unsigned(15 downto 0)); -- result end component; component slaveIn is port( scl_i, sda_i : in std_logic; -- I2C SCL, SDA input scl_o, sda_o : out std_logic; -- I2C SCL, SDA output devAddr_i : in std_logic_vector ( 6 downto 0); -- I2C address for this device is16Bits_i : in std_logic; -- register size, 1: 16 bits, 0: 8 bits data_o : out unsigned(15 downto 0)); -- register data output ( (7,0) for 8-bit register ) end component; component slaveOut is port( scl_i, sda_i : in std_logic; -- I2C SCL, SDA input scl_o, sda_o : out std_logic; -- I2C SCL, SDA output devAddr_i : in std_logic_vector ( 6 downto 0); -- I2C address for this device is16Bits_i : in std_logic; -- register size, 1: 16 bits, 0: 8 bits data_i : in unsigned(15 downto 0)); -- register data input ( (7,0) for 8-bit register ) end component; signal a, b, r : unsigned(15 downto 0); signal ctrl : unsigned(15 downto 0); signal scl_out, sda_out : std_logic_vector(0 to 3); begin input1: slaveIn port map(scl_i, sda_i, scl_out(0), sda_out(0), input1_addr, '1', a); input2: slaveIn port map(scl_i, sda_i, scl_out(1), sda_out(1), input2_addr, '1', b); control: slaveIn port map(scl_i, sda_i, scl_out(2), sda_out(2), control_addr, '0', ctrl); alu_inst: ALU port map(a, b, ctrl(3 downto 0), r); result: slaveOut port map(scl_i, sda_i, scl_out(3), sda_out(3), result_addr, '1', r); scl_o <= scl_out(0) and scl_out(1) and scl_out(2) and scl_out(3); sda_o <= sda_out(0) and sda_out(1) and sda_out(2) and sda_out(3); end I2C_ALU_impl;